Registros

1. Códigos

1.1. Registro básico (PIPO)

Con habilitaciónSin habilitación

module reg_rst_en #(
  parameter Width = 8
) (
  input                  clk_i,
  input                  rst_i,
  input                  en_i,
  input      [Width-1:0] d_i,
  output reg [Width-1:0] q_o
);

  always @(posedge clk_i, posedge rst_i) begin
    if (rst_i)
      q_o <= 0;
    else if (en_i)
      q_o <= d_i;
  end

endmodule

module reg_rst #(
  parameter Width = 8
) (
  input                  clk_i,
  input                  rst_i,
  input      [Width-1:0] d_i,
  output reg [Width-1:0] q_o
);

  always @(posedge clk_i, posedge rst_i) begin
    if (rst_i)
      q_o <= 0;
    else 
      q_o <= d_i;
  end

endmodule

1.2. Registro de corrimiento Serie-Paralelo (SIPO)

module sipo_reg #(
  parameter Width = 8
) (
  input              clk_i,
  input              rst_i,
  input              d_i,  
  input              en_i,
  output [Width-1:0] q_o
);  

  reg  [Width-1:0] reg_q;
  wire [Width-1:0] mux_d;

  assign mux_d = (en_i) ? {reg_q[Width-2:0], d_i} : reg_q;

  always @(posedge clk_i, posedge rst_i) begin
    if (rst_i)
      reg_q <= 0;
    else
      reg_q <= mux_d;
  end

  assign q_o = reg_q;

endmodule

1.3. Registro de corrimiento Paralelo-Serie (PISO)

module piso_reg #(
  parameter Width = 8   
) (
  input             rst_i,
  input             clk_i,
  input [Width-1:0] d_i,
  input       [1:0] op_i,
  output            q_o
);  

  reg [Width-1:0] mux_d, reg_q;

  always @(d_i, op_i, reg_q) begin
    case (op_i)
      2'b00   : mux_d = reg_q;
      2'b01   : mux_d = d_i;
      2'b10   : mux_d = {reg_q[Width-2:0], 1'b0};
      default : mux_d = 0;
    endcase
  end   

  always @(posedge clk_i, posedge rst_i) begin
    if (rst_i)
      reg_q <= 0;
    else
      reg_q <= mux_d;    
  end

  assign q_o = reg_q[Width-1];

endmodule