Flip-Flop¶ 1. Códigos¶ 1.1. D Flip-Flop básico¶ d_ff.v 1 2 3 4 5 6 7 8 9 10 11module d_ff ( input clk_i, input d_i, output reg q_o ); always @(posedge clk_i) begin q_o <= d_i; end endmodule 1.2. D Flip-Flop con reset¶ AsincrónoSíncrono d_ff_rst.v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15module d_ff_rst ( input clk_i, input rst_i, input d_i, output reg q_o ); always @(posedge clk_i, posedge rst_i) begin if (rst_i) q_o <= 1'b0; else q_o <= d_i; end endmodule d_ff_rst_sync.v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15module d_ff_rst_sync ( input clk_i, input rst_i, input d_i, output reg q_o ); always @(posedge clk_i) begin if (rst_i) q_o <= 1'b0; else q_o <= d_i; end endmodule 1.3. D Flip-Flop con reset y habilitación¶ AsincrónoSíncrono d_ff_rst_en.v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16module d_ff_rst_en ( input clk_i, input rst_i, input en_i, input d_i, output reg q_o ); always @(posedge clk_i, posedge rst_i) begin if (rst_i) q_o <= 1'b0; else if (en_i) q_o <= d_i; end endmodule d_ff_rst_en_sync.v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16module d_ff_rst_en_sync ( input clk_i, input rst_i, input en_i, input d_i, output reg q_o ); always @(posedge clk_i) begin if (rst_i) q_o <= 1'b0; else if (en_i) q_o <= d_i; end endmodule 2. Verificación¶ Proximamente ..