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Multiplexor

1. Códigos

1.1 Multiplexor 2 a 1 de n bits

mux2_to_1.v
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module mux2_to_1 #(
  parameter Width = 32
) (
  input  [Width-1:0] in1_i,
  input  [Width-1:0] in2_i,
  input              sel_i,
  output [Width-1:0] mux_o
);

  assign mux_o = sel_i ? in2_i : in1_i;

endmodule

1.1 Multiplexor 4 a 1 de n bits

mux4_to_1.v
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module mux4_to_1 #(
  parameter Width = 32
) (
  input  [Width-1:0] in1_i,
  input  [Width-1:0] in2_i,
  input  [Width-1:0] in3_i,
  input  [Width-1:0] in4_i,
  input        [1:0] sel_i,
  output [Width-1:0] out_o
);

  assign out_o = sel_i[1] ? (sel_i[0] ? in4_i : in3_i) : (sel_i[0] ? in2_i : in1_i);

endmodule
mux4_to_1_v2.v
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module mux4_to_1 #(
  parameter Width = 32
) (
  input      [Width-1:0] in1_i,
  input      [Width-1:0] in2_i,
  input      [Width-1:0] in3_i,
  input      [Width-1:0] in4_i,
  input            [1:0] sel_i,
  output reg [Width-1:0] out_o
);

  always @(in1_i, in2_i, in3_i, in4_i, sel_i) begin
    if (sel_i == 0) begin
      out_o = in1_i;
    end else if (sel_i == 1) begin
      out_o = in2_i;
    end else if (sel_i == 2) begin
      out_o = in3_i;
    end else if (sel_i == 3) begin
      out_o = in4_i;
    end else begin 
      out_o = 0;
    end
  end

endmodule
mux4_to_1_v3.v
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module mux4_to_1 #(
  parameter Width = 32
) (
  input      [Width-1:0] in1_i,
  input      [Width-1:0] in2_i,
  input      [Width-1:0] in3_i,
  input      [Width-1:0] in4_i,
  input            [1:0] sel_i,
  output reg [Width-1:0] out_o
);

  always @(in1_i, in2_i, in3_i, in4_i, sel_i) begin
    case (sel_i)
      2'd0    : out_o = in1_i;
      2'd1    : out_o = in2_i;
      2'd2    : out_o = in3_i;
      2'd3    : out_o = in4_i;
      default : out_o = 0;
    endcase
  end

endmodule